Enabling Interrupts

Core Interrupts

Three interrupt sources (Timer0, External Interrupt, and Interrupt on Change) have interrupt enable bits located in INTCON. These interrupts are referred to as 'core interrupts'.

To enable one of the core interrupts only the individual Interrupt Enable bit and the GIE bit need to be set.

Note: Clearing an Interrupt Request flag before setting the Interrupt Enable Flag prevents any pending interrupt requests from triggering an immediate interrupt.

Peripheral Interrupts

The PIC16F1xxx peripherals capable of generating interrupt requests each has their interrupt enable flags in one of the three PIE registers. To enable a peripheral interrupt the individual interrupt flag, GIE, and PEIE (peripheral interrupt enable) bits must all be set.