Interrupts

Enhanced mid-range PIC MCUs utilize a single vector pre-emptive interrupt structure.

Each peripheral on the PIC is capable of generating an interrupt request. When an interrupt request occurs and interrupts for the requesting device is enabled, an interrupt will occur.

The enhanced mid-range PIC uses a 16 level hardware stack to store the current content of the PC when an interrupt occurs. The program context is saved in shadow registers and control is passed to program memory address 0x04.

Interrupt Service Routine (ISR)

The user is responsible for writing the code to service the interrupt and placing the code at address 0x04. This Interrupt Service Routine (ISR) determines the source of the interrupt, then performs the necessary task to service the interrupting peripheral. An ISR's final instruction is the Return From Interrupt (RETFIE) instruction.

Automatic Context Saving

The following registers are saved to a single-level shadow register set in the event of an interrupt

• W register
• BSR
• STATUS
• FSR
• PCLATH

When the ISR executes the RETFIE instruction, these registers are restored to the pre-interrupt value

Single Level Interrupt Pre-emption

When an interrupt occurs the Global Interrupt Enable bit (GIE) in the status register is disabled. This will prevent an interrupt from being pre-empted by another interrupt.

Upon executing a RETFIE the state of the GIE control bit is restored to its pre-interrupt value.