Operational and Optimization Commands
These commands handle resets and basic operations.
Inherent Operations
| Mnemonic, Operands |
Description | Cycles | 14-bit Opcode MSb……LSb |
Status Affected |
Notes | |
|---|---|---|---|---|---|---|
| Inherent Operations | ||||||
| CLRWDT | Clear Watchdog Timer | 1 | 00 0000 0110 0100 | TO,PD | ||
| NOP | No Operation | 1 | 00 0000 0000 0000 | None | ||
| OPTION | Load OPTION register with W | 1 | 00 0000 0110 0010 | None | ||
| RESET | Software device Reset | 1 | 00 0000 0000 0001 | None | ||
| SLEEP | Go into standby mode | 1 | 00 0000 0110 0011 | TO, PD | ||
| TRIS | f | Load TRIS register | 1 | 00 0000 0110 0fff | None | |
These commands are for specific C Compilers.
C-Compiler Optimized
| Mnemonic, Operands |
Description | Cycles | 14-bit Opcode MSb……LSb |
Status Affected |
Notes | |
|---|---|---|---|---|---|---|
| C-Compiler Optimized | ||||||
| ADDFSR | Add Literal to FSRn | 1 | 11 0001 0nkk kkkk | None | ||
| MOVIW | Move Indirect FSRn to W | 1 | 00 0000 0001 0nnn | Z | 2 | |
| MOVWI | Move W to Indirect FSRn | 1 | 00 0000 0001 1nnnn | Z | 2 | |
Notes:
- If the program counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP
- If this instruction addresses an INDF register AND the MSb of the corresponding FSR is set, the instruction requires one additional instruction cycle.