Maintaining Cache Coherency Summary

The MPLAB XC32 C compiler’s runtime start-up code enables the cache and configures it for the highest performance (write-back with write allocation). This requires you to manage any potential cache coherency issues.

Any time two resources on a device depend on the same block of memory, you have to control access to that memory to ensure it isn’t simultaneously being changed by one and used by the other. A memory “ownership” flag can be created and used for this purpose.

In addition to controlling access to shared memory, you are also responsible for maintaining cache coherency.

There are three ways to achieve this:

1) Completely disable cache

2) Enable cache but disable the ability to cache shared data

3) Enable cache and manage cache coherency for shared data