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PIC32MZ Core Architecture
⭐(4,7)
Course Overview
Getting Started
Introduction
Introduction
MCU Introduction
CPU Overview
Instruction Pipeline
System Bus
microAptiv™/M5150 Core ISA
Overview
CPU Registers
Shadow Registers
Addressing Modes
Instruction Categories
Data Types
Endianness
Coprocessors
Memory Organization
Overview
Modes of Operation
Virtual Address Space
Virtual vs. Physical Memory
Address Translation
Memory Map Example
Alignment
Level 1 Cache
Prefetch Module
L1 Cache
What is Cache Memory?
How Does Cache Work?
Cache Coherency Defined
Managing Cache Coherency
Cache Policy Comparison Chart
Changing The Cache Policy
Cache Management Assembly Instructions
Completely Disable the Cache
Disable Cache for Shared Data
Maintaining Cache Coherency Summary
Exception Mechanism
PIC32MZ Exception Overview
Exception Types
Entry Points
Control Registers
Operation
Interrupt & Exception Usage
Processor Initialization
Project 1: Interrupt Code Example (in C)
Objective
Hardware Tools
Software Tools & Exercise Files
Procedure
Results
Conclusions
Project 2: General Exception Code Example (in C)
Objective
Hardware Tools
Software Tools & Exercise Files
Procedure
Results
Conclusions
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