Level 1 Cache

A CPU cache is a separate small block of memory used to compensate for the slower access time of main memory. A cache described as a Level 1 (L1) cache uses memory that is as fast as the CPU, so as long as the CPU is accessing the cache, it will never have to wait for an instruction or data. Level 2 and Level 3 caches are used in conjunction with a Level 1 cache and have memory whose access times are greater than the CPU, but are less than main memory. 

The PIC32MZ family uses an L1 cache only. The L1 cache is divided into two parts: an instruction cache and a data cache. Use of the cache is critical to achieving the maximum performance from the PIC32MZ family. Memory access to and from the cache always occurs in a single clock cycle. Accessing main memory could take three or more cycles.

Note that "Single cycle" refers to one instruction cycle which is one PBCLK7 clock cycle.

Application Note "AN1600" covers detailed use of L1 Cache memory on PIC32MZ devices.
 
Visit the L1 Cache Chapter which goes into further details on configuration/use of the L1 cache.

By default, MPLAB XC32 start-up code enables the cache and configures it in write-back with write allocation mode.
 
This policy is the easiest for the hardware to implement and consumes the least system bus resources and power. However, it is the least useful for keeping shared data coherent. Combining this cache policy with using uncached (KSEG1) memory for shared data is the simplest cache management approach, and is recommended for getting your project up and running.