M4K Core ISA Overview

The Instruction Set Architecture (ISA) of a Central Processing Unit (CPU) refers to the lowest-level interface between the programmer and the CPU, and includes the following aspects:

• Data types
  • Supported operand representations
• Operations on data
  • Arithmetic/other operations that can be performed on the operands
• Instruction format
• Memory organization
• Addressing modes

ISAs are also often referred to as the "Programmers Model" of a CPU.

PIC32MX, with the MIPS32 M4K CPU core, implements Release 2 of the MIPS32 architecture in a 5-stage pipeline. It includes the MIPS16e™ Application-Specific Extension (ASE), which improves code density through the use of 16-bit encodings of MIPS32 instructions plus some MIPS16e-specific instructions.

This ISA may be classified as a Load/Store or Register-Register type (i.e. ALU operations act on register operands only - no memory references). On modern CPUs, this is done to decouple CPU speed from main memory speed.

Refer to MIPS® Architecture For Programmers Volume I-A: Introduction to the MIPS32® Architecture for more information on the CPU Programming Model for the MIPS32 core.