Data Write Saturation
Data Write Saturation is a useful feature when Normal Saturation is not in use. As we have seen earlier, when Super Saturation is enabled or Saturation is disabled, the guard bits in Accumulator Upper are utilized to store magnitude data. Yet, when we store the contents of the accumulator with SAC, SAC.R, or with Accumulator Write Back, the source is the Accumulator High register. If no shifting is performed, Accumulator Upper is ignored when the value is stored in memory. To accommodate for this situation, Data Write Saturation will store the best possible 16-bit value from the 40-bit accumulator.
- When using 9.31 (super) saturation, the magnitude information in the guard bits would be ignored when storing to the W registers.
- Data Write Saturation saturates the destination register based on the magnitude information in the ACCxU.
- For SAC, SAC.R, and Accumulator Write-Back, the 1.15 saturated contents of ACCxH are stored in 16-bit memory.
- This mode is enabled by the CORCON:<SATDW> bit.
Data Write Saturation Control
If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly. For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions.
CORCON: Core Control Register
| U-0 | U-0 | U-0 | R/W-0 | R/W-0 | R-0 | R-0 | R-0 |
| — | — | — | US | EDT | DL2 | DL1 | DL0 |
| bit 15 | bit 8 |
| R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/C-0 | R/W-0 | R/W-0 | R/W-0 |
| SATA | SATB | SATDW | ACCSAT | IPL3 | PSV | RND | IF |
| bit 7 | bit 0 |
| Legend | ||
| R = Readable Bit | W = Writable Bit | U = Unimplemented bit, read as '0' |
| u = Bit is unchanged | x = bit is unknown | -n/n = Value at POR and BOR/Value at all other resets |
| '1' = bit is set | '0' = bit is cleared | -n = Value at POR reset |
bit 15-13 Unimplemented: Read as '0
bit 12 US: DSP Multiply Unsigned/Signed Control bit
bit 11 EDT: Early DO Loop Termination Control bit
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
bit 7 SATA: AccA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
bit 6 SATB: AccB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3
bit 2 PSV: Program Space Visibility in Data Space Enable bit
bit 1 RND: Rounding Mode Select bit
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
Examples
In this first example, the value stored to W0 is 0x7FFF, since Accumulator A is positive and larger than 32-bits.
SAC.R A,W0 ;Store ACCA to W0
if ACCA = 0x010FFF1234
then W0 = 0x7FFF ;if SATDW enabled
else W0 = 0x0FFF ;if SATDW disabled
In the second example, the value stored to W13 in the Accumulator Write Back of the MAC instruction is 0x8000, since Accumulator B is negative and larger than 32-bits.
MAC W4*W5,A,W13 ;Stores ACCB to W13
If ACCB = 0x9B07644410
The value stored to W13 = 0x8000