Output Control

Output Pin Enable

Each CWG output pin has an individual output pin enable control. The output enables are selected with the GxOEA and GxOEB bits of the CWGxCON0 register. When an output pin enable is cleared, the CWG has no connection to the output pin. When the output enable is set, the override value or active PWM waveform is applied to the pin per the internal port priority selection.

The CWG function can be completely disabled by clearing the GxEN pin in the CWGxCON0 register.

Polarity Control

The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active high. Clearing the output polarity bit configures the corresponding output as active low. However, polarity does not affect override levels. Output polarity is selected with the GxPOLA and GxPOLB bits of the CWGxCON0 register.