Academic Program

Data Gating

Data Gating

The Data Gating section has four logic gates that need to be set up. This requires five separate registers to be set up. They configure the inverted or non-inverted connection from the inputs that control the CLC peripheral. The five registers include:

  • CLCxGLS0
  • CLCxGLS1
  • CLCxGLS2
  • CLCxGLS3
  • CLCxPOL

Each gate starts off as a base OR gate, but each input and output can be individually inverted or not inverted.
This allows AND, NAND, OR, and NOR gates to be created. The gates can also be set up to drive a constant 1 or 0 logic level.

datagating.png

 

Each input to a data gate has a pair of bits in one of the CLCxGLSx registers. The two bits include a non-inverted (T) bit and an inverted (N) bit that needs to be set up. If the T bit is set, then the input is non-inverted. If the N bit is set, then the input is inverted. If both are set to zero, then the input is not connected to the gate.

clcglsregisters.png

 

The CLCxPOL register bit, LCxGxPOL bit, will invert or not invert the output of the gate.
0 - non-inverted
1 - inverted